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19-3165; Rev 0; 1/04
KIT ATION EVALU BLE AVAILA
Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output
General Description
The MAX1549 dual pulse-width modulation (PWM) stepdown controller provides the high efficiency, excellent transient response, and high DC-output accuracy necessary for generating low-voltage chipset and RAM power supplies in notebook computers. The controller employs a fixed-frequency, current-mode PWM architecture that does not require complex compensation. The MAX1549 also interleaves the dual step-down regulators, minimizing the input capacitor requirements. The MAX1549 features differential current-sense inputs for accurately sensing the inductor current across an external current-sense resistor in series with the output to ensure reliable overload protection. Alternatively, the controller can provide overload protection using lossless inductor current-sensing methods, lowering power dissipation and reducing system cost. Single-stage buck conversion allows the MAX1549 to directly step down high-voltage batteries for the highest possible efficiency. Very low output-voltage applications require two-stage conversion--stepping down from another system supply rail instead of the battery. The MAX1549 powers chipsets and graphics processor cores that require dynamically adjustable output voltages, or generates the active termination bus that must track the input reference. The main step-down controller (OUT1) regulates the dedicated reference input (REFIN) voltage generated by a resistive voltage-divider from the MAX1549's reference. The MAX1549 also includes internal open-drain pulldowns with logic-level control inputs to dynamically adjust the REFIN resistive-divider ratio. When a transition occurs on these control inputs, the controller enters forced-PWM mode and blanks the power-good (PGOOD1) output and output fault protection. OUT2 uses a Dual-ModeTM feedback input to provide either fixed 2.5V/1.8V or adjustable output voltage regulation. The MAX1549 is available in a 40-pin, 6mm x 6mm thin QFN package.
Features
Interleaved, Fixed-Frequency, Current-Mode Control Architecture 1% VOUT Accuracy Over Line and Load Main Output (OUT1) 0.5V to 2.0V Adjustable Output External Reference Input for Dynamically Selectable Output Voltages Four Digitally Selectable Output Voltages Power-Good and Fault Blanking During Transitions Second Output (OUT2) 2.5V/1.8V Fixed or 0.5V to 2.7V Adjustable Output Accurate Differential Current-Sense Inputs 100kHz/200kHz/300kHz/400kHz Selectable Switching Frequency Output Overvoltage/Undervoltage Protection Soft-Start and Soft-Shutdown Drives Large Synchronous-Rectifier FETs 2V 0.6% Reference Output Separate Enable Inputs with Accurate Threshold Voltages Separate Power-Good Window Comparators
MAX1549
Ordering Information
PART MAX1549ETL TEMP RANGE -40C to +85C PIN-PACKAGE 40 Thin QFN 6mm x 6mm
Pin Configuration
PGOOD1
Applications
Notebook Computers Dynamically Adjustable Chipset Supplies Video/GPU Core Supplies DDR Memory Termination CPU Core or VCC Supplies Fixed Chipset/RAM Supplies Active Termination Buses
TOP VIEW
REFIN CSH1 OUT1 CSL1 OD3 OD2 OD1
40 39 38 37 36 35 34 33 32 31
N.C.
DH1
GND N.C. REF VCC CC1 ILIM1 ILIM2 G0 G1 FBLANK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
30 29 28 27
LX1 BST1 SKIP DL1 VDD N.C. DL2 PGND BST2 LX2
MAX1549
26 25 24 23 22 21
PGOOD2
FSEL
CSH2
CSL2
OUT2
Dual Mode is a trademark of Maxim Integrated Products, Inc.
THIN QFN 6mm x 6mm
________________________________________________________________ Maxim Integrated Products
N.C.
ON1
ON2
FB2
DH2
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output MAX1549
ABSOLUTE MAXIMUM RATINGS
VCC to GND ..............................................................-0.3V to +6V VDD to PGND............................................................-0.3V to +6V CSH_, CSL_, OUT_, PGOOD_, OD_ to GND ...........................................-0.3V to (VCC + 0.3V) G0, G1, ILIM_, REFIN to GND ..................................-0.3V to +6V FB2, SKIP, ON_ to GND ...........................................-0.3V to +6V REF, CC1, FBLANK, FSEL to GND.............-0.3V to (VCC + 0.3V) DL1, DL2 to PGND .....................................-0.3V to (VDD + 0.3V) BST1, BST2 to PGND .............................................-0.3V to +36V LX1 to BST1..............................................................-6V to +0.3V DH1 to LX1 ..............................................-0.3V to (VBST1 + 0.3V) LX2 to BST2..............................................................-6V to +0.3V DH2 to LX2 ..............................................-0.3V to (VBST2 + 0.3V) GND to PGND .......................................................-0.3V to +0.3V REF Short Circuit to GND ...........................................Continuous Continuous Power Dissipation (TA = +70C) 40-Pin 6mm x 6mm Thin QFN (derated 26.3mW/C above +70C).............................................................2105mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VCC = VDD = 5V, SKIP = GND, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER INPUT SUPPLIES (Note 1) Input Voltage Range Quiescent Supply Current (VCC) Quiescent Supply Current (VDD) Shutdown Supply Current (VCC) Shutdown Supply Current (VDD) PWM CONTROLLERS Main Output-Voltage Accuracy (OUT1 Tracking) VREFIN VOUT1 With respect to REFIN, SKIP = VCC or GND 50% duty cycle 10% to 90% duty cycle -5 -10 2.475 1.780 0.490 0.485 0.1 1 0.5 0.5 -1 -0.1 120 85 250 180 2.0 2.7 +1 +0.1 460 335 2.5 1.8 0.50 0 +5 mV +10 2.525 1.820 0.510 0.515 V V % % V A A k VBIAS ICC IDD VCC, VDD OUT1 and FB2 forced above their regulation points OUT1 and FB2 forced above their regulation points ON1 = ON2 = GND, SKIP = VCC ON1 = ON2 = GND 4.5 1.0 1.5 2.5 <1 5.5 1.8 5 5 5 V mA A A A SYMBOL CONDITIONS MIN TYP MAX UNITS
Secondary Preset Output-Voltage Accuracy (OUT2 Fixed) Secondary Feedback-Voltage Accuracy (FB2 Adjustable) Load-Regulation Error VIN Line-Regulation Error Output Adjust Range OUT1 Input Bias Current FB2 Input Bias Current OUT2 Input Resistance
VOUT2 VFB2
SKIP = VCC, 50% FB2 = GND duty cycle (Note 1) FB2 = VCC 50% duty cycle SKIP = VCC (Note 1) 10% to 90% duty cycle ILOAD = 0 to 3A, SKIP = VCC VIN = 2V to 28V OUT1 (tracks REFIN) OUT2
IOUT1 IFB2 ROUT2
VOUT1 = 0.5V to 2.0V VFB2 = 0 to 2.7V FB2 = GND or adjustable FB2 = VCC
2
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Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VCC = VDD = 5V, SKIP = GND, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER OUT_ Discharge-Mode On-Resistance OUT_ Synchronous-Rectifier Discharge-Mode Turn-On Level FSEL = GND Operating Frequency fOSC (Note 2) FSEL = REF FSEL = open FSEL = VCC Minimum On-Time Maximum Duty Cycle Soft-Start Ramp Time REFERENCE (REF) Reference Voltage Reference Load Regulation REF Lockout Voltage REFIN Voltage Range REFIN Input Bias Current FAULT DETECTION Output Overvoltage Trip Threshold Output Overvoltage Fault-Propagation Delay Output Undervoltage-Protection Trip Threshold Output Undervoltage-Protection Blanking Time Output Undervoltage Fault-Propagation Delay PGOOD_ Lower Trip Threshold PGOOD_ Upper Trip Threshold PGOOD_ Propagation Delay PGOOD_ Output Low Voltage PGOOD_ Leakage Current IPGOOD_ tPGOOD_ tBLANK tUVP With respect to error-comparator threshold, hysteresis = 1% With respect to error-comparator threshold, hysteresis = 1% OUT1 and FB2 forced 2% beyond PGOOD_ trip threshold ISINK = 4mA OUT1 = REFIN and VFB2 = 0.5V (PGOOD_ high impedance), PGOOD_ forced to 5.5V -12.5 +7.5 tOVP With respect to error-comparator threshold OUT1 and FB2 forced 2% above trip threshold With respect to error-comparator threshold From rising edge of ON_ 65 12 14.5 10 70 4096 / fOSC 10 -10 +10 10 0.3 1 -7.5 +12.5 75 17 % s % s s % % s V A VREF VREF VREFIN IREFIN VCC = 4.5V to 5.5V, IREF = 0 TA = +25C TA = 0C to +85C 1.988 1.985 1.980 1.95 0.5 -50 2.0 +50 2.00 2.00 2.012 2.015 2.020 V V V V nA tON(MIN) DMAX tSS Measured from the rising edge of ON_ to full scale (Note 3) 91 93 512 / fOSC SYMBOL RDISCHARGE 0.2 70 170 270 350 CONDITIONS MIN TYP 12 0.3 100 200 300 400 MAX 40 0.4 130 230 330 450 200 ns % s kHz UNITS V
MAX1549
IREF = -10A to +100A
VREF(UVLO) Rising edge, hysteresis = 350mV
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Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output MAX1549
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VCC = VDD = 5V, SKIP = GND, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Fault-Blanking Time Thermal-Shutdown Threshold VCC Undervoltage-Lockout Threshold CURRENT LIMIT ILIM_ Adjustment Range Current-Limit Input Range CSH_/CSL_ Input Bias Current Current-Limit Threshold (Fixed) Current-Limit Threshold (Adjustable) Current-Limit Threshold (Zero Crossing) VLIMIT VLIMIT VCSH_, VCSL _ VCSH_ = VCSL _ = 0 to 2.7V VCSH_ - VCSL _, ILIM_ = VCC VILIM_ = 2.0V VCSH_ - VCSL _ VILIM_ = 1.0V VILIM_ = 0.5V VZX VPGND - VLX_, SKIP = GND ILIM_ = VCC Idle-ModeTM Threshold VCSH_ - VCSL _ With respect to current-limit threshold -0.1 RDH RDL IDH BST_ - LX_ forced to 5V DL_, high state DL_, low state DH_ forced to 2.5V, BST_ - LX_ forced to 5V 1.5 1.5 0.5 1 1 3 35 26 10 OD_ high impedance, VOD_ = 5.5V Rising edge, hysteresis = 600mV SKIP, G0, G1 hysteresis = 600mV High Low 2.4 2.4 0.8 2.6 100 100 2.8 10 0.25 0 -0.15 65 170 91 42 70 200 100 50 3 15 20 +0.1 6 6 2.7 20 VREF 2.7 +0.15 75 230 109 58 mV mV % A A A A ns mV V V A mV SYMBOL tFBLANK TSHDN VCC(UVLO) CONDITIONS FBLANK = VCC FBLANK = open FBLANK = REF Hysteresis = 15C Rising edge, PWM disabled below this level, hysteresis = 50mV 4.1 MIN 110 60 22 TYP 150 100 50 +165 4.25 4.4 MAX 190 140 75 C V s UNITS
ILIM_ Leakage Current GATE DRIVERS DH_ Gate-Driver On-Resistance DL_ Gate-Driver On-Resistance DH_ Gate-Driver Source/Sink Current DL_ Gate-Driver Source Current DL_ Gate-Driver Sink Current Dead Time INPUTS AND OUTPUTS OD_ On-Resistance OD_ Leakage Current ON_ Logic Input Threshold Logic Input Voltage ROD_ IOD_
IDL (SOURCE) DL_ forced to 2.5V IDL (SINK) tDEAD DL_ forced to 2.5V DL_ rising DH_ rising
nA V V
Idle Mode is a trademark of Maxim Integrated Products, Inc.
4
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Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VCC = VDD = 5V, SKIP = GND, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Logic Input Current Dual-Mode Threshold Voltage SYMBOL CONDITIONS ON_, SKIP, G0, G1 FB2 High Low High Four-Level Input Logic Levels FSEL, FBLANK Open REF Low Four-Level Logic Input Current FSEL, FBLANK forced to GND or VCC -3 MIN -1 1.9 0.05 VCC 0.4V 3.15 1.65 2.0 0.1 TYP MAX +1 2.1 0.15 UNITS A V
MAX1549
3.85 2.35 0.5 +3
V
A
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VCC = VDD = 5V, SKIP = GND, TA = -40C to +85C, unless otherwise noted.) (Note 4)
PARAMETER INPUT SUPPLIES (Note 1) Input Voltage Range Quiescent Supply Current (VCC) Quiescent Supply Current (VDD) Shutdown Supply Current (VCC) Shutdown Supply Current (VDD) PWM CONTROLLERS Main Output-Voltage Accuracy (OUT1 Tracking) Secondary Preset Output-Voltage Accuracy (OUT2 Fixed) Secondary Feedback-Voltage Accuracy (FB2 Adjustable) Output Adjust Range OUT2 Input Resistance OUT_ Discharge-Mode On-Resistance OUT_ Synchronous-Rectifier Discharge-Mode Turn-On Level ROUT2 RDISCHARGE 0.2 VREFIN VOUT1 VOUT2 VFB2 With respect to 50% duty cycle REFIN, SKIP = VCC 10% to 90% duty cycle or GND SKIP = VCC, 50% duty cycle (Note 1) SKIP = VCC (Note 1) OUT1 (tracks REFIN) OUT2 FB2 = GND or adjustable FB2 = VCC FB2 = GND FB2 = VCC 50% duty cycle 10% to 90% duty cycle -8 -10 2.470 1.775 0.490 0.485 0.5 0.5 120 85 +8 mV +10 2.530 1.825 0.510 0.515 2.0 2.7 460 335 40 0.4 V V V k V VBIAS ICC IDD VCC, VDD OUT1 and FB2 forced above their regulation points OUT1 and FB2 forced above their regulation points ON1 = ON2 = GND, SKIP = VCC ON1 = ON2 = GND 4.5 5.5 1.8 5 5 5 V mA A A A SYMBOL CONDITIONS MIN MAX UNITS
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5
Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output MAX1549
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VCC = VDD = 5V, SKIP = GND, TA = -40C to +85C, unless otherwise noted.) (Note 4)
PARAMETER SYMBOL CONDITIONS FSEL = GND Operating Frequency fOSC (Note 2) FSEL = REF FSEL = open FSEL = VCC Maximum Duty Cycle REFERENCE (REF) Reference Voltage Reference Load Regulation REFIN Voltage Range FAULT DETECTION Output Overvoltage Trip Threshold Output Undervoltage-Protection Trip Threshold PGOOD_ Lower Trip Threshold PGOOD_ Upper Trip Threshold PGOOD_ Output Low Voltage Fault-Blanking Time VCC Undervoltage-Lockout Threshold CURRENT LIMIT ILIM_ Adjustment Range Current-Limit Input Range Current-Limit Threshold (Fixed) Current-Limit Threshold (Adjustable) Idle-Mode Threshold GATE DRIVERS DH_ Gate-Driver On-Resistance DL_ Gate-Driver On-Resistance RDH RDL BST_ - LX_ forced to 5V DL_, high state DL_, low state 6 6 2.7 VLIMIT VLIMIT VCSH_, VCSL _ VCSH_ - VCSL _, ILIM_ = VCC VILIM_ = 2.0V VCSH_ - VCSL _ VILIM_ = 1.0V VILIM_ = 0.5V VCSH_ - VCSL _, ILIM_ = VCC 0.25 0 65 170 89 42 10 VREF 2.7 75 230 111 58 20 mV mV V V mV tFBLANK With respect to error-comparator threshold With respect to error-comparator threshold With respect to error-comparator threshold, hysteresis = 1% With respect to error-comparator threshold, hysteresis = 1% ISINK = 4mA FBLANK = VCC FBLANK = open FBLANK = REF VCC(UVLO) Rising edge, PWM disabled below this level, hysteresis = 50mV 110 60 22 4.1 12 65 -12.5 +7.5 17 75 -7.5 +12.5 0.3 190 140 75 4.4 V s % % % % V VREF VREF VCC = 4.5V to 5.5V, IREF = 0 IREF = -10A to +100A 1.985 1.980 0.5 2.015 2.020 2.0 V V V DMAX MIN 70 170 270 350 91 MAX 130 230 330 450 % kHz UNITS
6
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Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VCC = VDD = 5V, SKIP = GND, TA = -40C to +85C, unless otherwise noted.) (Note 4)
PARAMETER INPUTS AND OUTPUTS OD_ On-Resistance ON_ Logic Input Threshold Logic Input Voltage Dual-Mode Threshold Voltage ROD_ Rising edge, hysteresis = 600mV SKIP, G0, G1, hysteresis = 600mV FB2 High Low High Low High Four-Level Input Logic Levels FSEL, FBLANK Open REF Low 1.9 0.05 VCC - 0.4V 3.15 1.65 3.85 2.35 0.5 V 2.4 2.4 0.8 2.1 0.15 100 2.8 V V V SYMBOL CONDITIONS MIN MAX UNITS
MAX1549
Note 1: When the inductor is in continuous conduction, the output voltage has a DC regulation level lower than the error-comparator threshold by 50% of the ripple. In discontinuous conduction (SKIP = GND, light load), the output voltage has a DC regulation level higher than the trip level by approximately 1.5% due to slope compensation. Note 2: The MAX1549 cannot operate over all combinations of frequency, input voltage (VIN), and output voltage. For large input-tooutput differentials and high switching-frequency settings, the required on-time may be too short to maintain the regulation specifications. Under these conditions, a lower operating frequency must be selected. The minimum on-time must be greater than 150ns, regardless of the selected switching frequency. On-time and off-time specifications are measured from the 50% point to the 50% point at the DH_ pin with LX_ = GND, VBST_ = 5V, and a 250pF capacitor connected from DH_ to LX_. Actual in-circuit times may differ due to MOSFET switching speeds. Note 3: Specifications are guaranteed by design, not production tested. Note 4: Specifications to -40C are guaranteed by design, not production tested.
Typical Operating Characteristics
(MAX1549 circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, SKIP = GND, FSEL = open, TA = +25C, unless otherwise noted.)
OUT1 EFFICIENCY vs. LOAD CURRENT (VOUT1 = 1.0V)
MAX1549 toc01
1.0V OUTPUT VOLTAGE (OUT1) vs. LOAD CURRENT
MAX1549 toc02
OUT2 EFFICIENCY vs. LOAD CURRENT (VOUT2 = 2.5V)
SKIP = GND SKIP = VCC
MAX1549 toc03
100 SKIP = GND SKIP = VCC
1.05 1.04 OUTPUT VOLTAGE (V) 1.03 SKIP = GND SKIP = VCC
100
90 EFFICIENCY (%)
90 EFFICIENCY (%)
80 VIN = 5V VIN = 12V 60 VIN = 20V 50 0.01 0.1 1 10 LOAD CURRENT (A)
1.02 1.01 1.00
80 VIN = 5V 70 VIN = 12V VIN = 20V
70
60 0.99 0.98 0 1 2 3 4 5 6 7 LOAD CURRENT (A) 50 0.01 0.1
1
10
LOAD CURRENT (A)
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7
Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output MAX1549
Typical Operating Characteristics (continued)
(MAX1549 circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, SKIP = GND, FSEL = open, TA = +25C, unless otherwise noted.)
2.5V OUTPUT VOLTAGE (OUT2) vs. LOAD CURRENT
MAX1549 toc04
1.0V OUTPUT VOLTAGE (OUT1) vs. INPUT VOLTAGE
MAX1549 toc05
IDLE-MODE CURRENT vs. INPUT VOLTAGE
4.0 3.5 PEAK CURRENT (A) 3.0 2.5 2.0 1.5 1.0 0.5 1.0V OUTPUT
MAX1549 toc06
1.02 SKIP = GND SKIP = VCC OUTPUT VOLTAGE (V) 1.01
4.5
2.59 2.57 OUTPUT VOLTAGE (V) 2.55 2.53 2.51 2.49 2.47 2.45 0
SKIP = GND SKIP = VCC
1.00
0.99
0.98 1 2 3 4 5 6 7 0 5 10 INPUT VOLTAGE (V) 15 20 LOAD CURRENT (A)
0 0 4 8 12 16 20 INPUT VOLTAGE (V)
2.5V OUTPUT VOLTAGE (OUT2) vs. INPUT VOLTAGE
MAX1549 toc07
IDLE-MODE CURRENT vs. INPUT VOLTAGE
MAX1549 toc08
SUPPLY CURRENT vs. INPUT VOLTAGE (FORCED-PWM OPERATION)
MAX1549 toc09
2.60 SKIP = GND SKIP = VCC 2.57 OUTPUT VOLTAGE (V)
2.5
2.0 PEAK CURRENT (A)
DUTY CYCLE LIMITED
28 24 SUPPLY CURRENT (mA) 20 16 12 8 4 NO LOAD SKIP = ON1 = ON2 = VCC 0 4 8 12 16 IIN IBIAS
2.54
1.5
2.51
1.0
2.48
0.5 2.5V OUTPUT
2.45 0 5 10 INPUT VOLTAGE (V) 15 20
0 0 4 8 12 16 20 INPUT VOLTAGE (V)
0 20 INPUT VOLTAGE (V)
SUPPLY CURRENT vs. INPUT VOLTAGE (PULSE-SKIPPING OPERATION)
MAX1549 toc10
2.0V REFERENCE LOAD REGULATION
MAX1549 toc11
REFERENCE DISTRIBUTION
SAMPLE SIZE = 150 SAMPLE PERCENTAGE (%) 40
MAX1549 toc12
1.4 IBIAS 1.2 SUPPLY CURRENT (mA) 1.0 IIN 0.8 0.6 0.4 0.2 0 0 4 8 12 16 1mA LOAD SKIP = GND ON1 = ON2 = VCC
4 REFERENCE VOLTAGE DEVIATION (mV) 3 2 1 0 -1 -2 -3 -4 -20 0 20 40 60 80
50
30
20
10
20
100
0 1.990
1.995
2.000
2.005
2.010
INPUT VOLTAGE (V)
REFERENCE LOAD CURRENT (A)
REFERENCE VOLTAGE (V)
8
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Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output MAX1549
Typical Operating Characteristics (continued)
(MAX1549 circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, SKIP = GND, FSEL = open, TA = +25C, unless otherwise noted.)
SWITCHING FREQUENCY DISTRIBUTION (300kHz OPERATION)
SAMPLE SIZE = 150 SAMPLE PERCENTAGE (%) 40
MAX1549 toc13
STARTUP WAVEFORM (HEAVY LOAD)
MAX1549 toc14
STARTUP WAVEFORM (LIGHT LOAD)
MAX1549 toc15
50
5V A 0 2.5V B 0
5V A 0 2.5V B 0 C 2A 0 D 400s/div 0 200s/div A: ON2, 5V/div B: 2.5V OUTPUT, 2V/div 100 LOAD C: INDUCTOR CURRENT, 2A/div D: PGOOD2, 5V/div D C
30
20
5A 0 0 290 295 300 305 310
10
0 SWITCHING FREQUENCY (kHz)
A: ON2, 5V/div B: 2.5V OUTPUT, 2V/div 0.5 LOAD
C: INDUCTOR CURRENT, 5A/div D: PGOOD2, 5V/div
SHUTDOWN WAVEFORM (1 LOAD)
MAX1549 toc16
SHUTDOWN WAVEFORM (100 LOAD)
MAX1549 toc17
INTERLEAVED OPERATION
MAX1549 toc18
5V 0 2.5V
A
5V 0 2.5V
A
12V A 0
B 0 5V C 0 0 5V 0 100s/div A: ON2, 5V/div B: OUT2, 2V/div C: DL2, 5V/div D: INDUCTOR CURRENT, 5A/div E: PGOOD2, 5V/div A: ON2, 5V/div B: OUT2, 2V/div C: DL2, 5V/div D E 0 5V 0 0 5V 0 1ms/div
B
1.0V
B
C D E
12V C 0 2.5V D
2s/div A: LX1, 10V/div C: LX2, 10V/div B: 1.0V OUTPUT, 50mV/div D: 2.5V OUTPUT, 50mV/div
D: INDUCTOR CURRENT, 2A/div E: PGOOD2, 5V/div
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9
Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output MAX1549
Typical Operating Characteristics (continued)
(MAX1549 circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, SKIP = GND, FSEL = open, TA = +25C, unless otherwise noted.)
2.5V OUTPUT LOAD TRANSIENT (FORCED PWM)
MAX1549 toc19
2.5V OUTPUT LOAD TRANSIENT (PULSE SKIPPING)
MAX1549 toc20
OUTPUT OVERLOAD (UVP ENABLED)
MAX1549 toc21
4A 0 2.55V 2.50V 2.45V 4A C 0 12V D 0 40s/div A: IOUT2 = 0 TO 4A, 5A/div C: INDUCTOR CURRENT, 5A/div B: VOUT2 = 2.5V, 100mV/div D: LX2, 10V/div SKIP = VCC A
4A A 0 B 2.55V 2.50V 4A 0 12V D 0 20s/div A: IOUT2 = 0.2A TO 4A, 5A/div C: INDUCTOR CURRENT, 5A/div B: VOUT2 = 2.5V, 50mV/div D: LX2, 10V/div SKIP = GND C B
5V 0 10A 0 2.5V 0 5A 0 5V 0 40s/div A: PGOOD2, 5V/div D: INDUCTOR CURRENT, 5A/div B: LOAD (2.5A TO 10A), 10A/div E: DL2, 5V/div C: 2.5V OUTPUT, 2V/div E B C D A
MAX1549 DYNAMIC OUTPUT VOLTAGE TRANSITION (CREFIN = 100pF)
3.3V 0 1.5V 1.0V 1.5V 1.0V 12V 0 5A 0 -5A 40s/div
MAX1549 toc22
MAX1549 DYNAMIC OUTPUT VOLTAGE TRANSITION (CREFIN = 1nF)
A B 1.0V 1.5V C 1.0V 12V D 0 2.5A 0 -2.5A 100s/div 3.3V 0 1.5V
MAX1549 toc23
A B
C
D
E
E
A: GATE, 5V/div D: LX1, 10V/div B: REFIN1, 0.5V/div E: INDUCTOR CURRENT, 10A/div C: OUT1 (1.0V TO 1.5V), 0.5V/div 200mA LOAD, SKIP = GND
A: GATE, 5V/div D: LX1, 10V/div B: REFIN1, 0.5V/div E: INDUCTOR CURRENT, 5A/div C: OUT1 (1.0V TO 1.5V), 0.5V/div 200mA LOAD, SKIP = GND
10
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Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output
Pin Description
PIN 1 2, 20, 25, 31 NAME GND N.C. FUNCTION Analog Ground. Connect backside pad to GND. Not Internally Connected 2.0V Reference Voltage Output. Bypass to analog ground with a 0.1F or greater ceramic capacitor. The reference can source up to 100A for external loads. Loading REF degrades output voltage accuracy according to the REF load-regulation error. The reference shuts down when both MAX1549 outputs are disabled. Analog Supply Input. Connect to the system supply voltage (+4.5V to +5.5V) through a series 20 resistor. Bypass VCC to analog ground with a 1F or greater ceramic capacitor. Integrator Capacitor Connection. Connect a 47pF to 1000pF (470pF typ) capacitor from CC1 to analog ground (GND) to set the integration time constant for the main MAX1549 controller (OUT1). Current-Limit Threshold Adjustment for Controller 1. The current-limit threshold defaults to 70mV if ILIM1 is connected to VCC. In adjustable mode, the current-limit threshold across CSH1 and CSL1 is precisely 1/10th the voltage seen at ILIM1 over a 0.5V to 2.0V range. The logic threshold for switchover to the 70mV default value is approximately VCC - 1V. Current-Limit Threshold Adjustment for Controller 2. The current-limit threshold defaults to 70mV if ILIM2 is connected to VCC. In adjustable mode, the current-limit threshold across CSH2 and CSL2 is precisely 1/10th the voltage seen at ILIM2 over a 0.5V to 2.0V range. The logic threshold for switchover to the 70mV default value is approximately VCC - 1V. Buffered N-Channel MOSFET Gate Inputs. See Table 4. Fault-Blanking Select Input. This four-level logic input enables or disables fault blanking and sets the minimum forced-PWM operation time (tFBLANK). When fault blanking is enabled, the MAX1549 blanks the PGOOD1 output and main (OUT1) controller's OVP/UVP fault protection for the selected time period after the controller detects a transition on G0 or G1. Additionally, the main controller enters forced-PWM mode for the duration of tFBLANK anytime G0 or G1 changes states. OUT1 fault protection and PGOOD1 blanking: VCC = 150s, open = 100s, REF = 50s, GND = blanking disabled Automatic forced-PWM transition operation (OUT1 only): VCC = 150s, open = 100s, REF = 50s, GND = 100s Frequency-Select Input. This four-level logic input sets the controller's switching frequency. Connect to GND, REF, VCC, or leave FSEL unconnected (open) to select the following typical switching frequencies: VCC = 400kHz, open = 300kHz, REF = 200kHz, GND = 100kHz OUT1 Enable Input. Pull to GND to shut down controller 1 (OUT1). Connect to VCC for normal operation. The output is discharged through a 12 resistor between OUT1 and GND, and DL1 is forced high after VOUT1 drops below 0.3V. A rising edge on ON1 or ON2 clears the fault-protection latch. OUT2 Enable Input. Pull to GND to shut down controller 2 (OUT2). Connect to VCC for normal operation. The output is discharged through a 12 resistor between OUT2 and GND, and DL2 is forced high after VOUT2 drops below 0.3V. A rising edge on ON1 or ON2 clears the fault-protection latch. Positive Current-Sense Input for Controller 2. Connect to the positive terminal of the current-sense element. Figure 8 describes current-sensing options. The PWM controller does not begin a cycle unless the current sensed is less than the current-limit threshold programmed at ILIM2.
MAX1549
3
REF
4 5
VCC CC1
6
ILIM1
7
ILIM2
8, 9
G0, G1
10
FBLANK
11
FSEL
12
ON1
13
ON2
14
CSH2
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Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output MAX1549
Pin Description (continued)
PIN 15 NAME CSL2 FUNCTION Negative Current-Sense Input for Controller 2. Connect to the negative terminal of the current-sense element. Figure 8 describes current-sensing options. The PWM controller does not begin a cycle unless the current sensed is less than the current-limit threshold programmed at ILIM2. Dual-Mode Feedback Input for Controller 2. Connect to VCC for a +1.8V fixed output or to analog ground (GND) for a +2.5V fixed output. For an adjustable output (0.5V to 2.7V), connect FB2 to a resistive divider from OUT2. The FB2 regulation level is +0.5V. Output Voltage-Sense Connection for Controller 2. Connect directly to the positive terminal of the output capacitors as shown in the Standard Applications Circuit (Figure 1). OUT2 senses the output voltage to determine the on-time for the high-side switching MOSFET. OUT2 also serves as the feedback input when using the preset internal output voltages as shown in Figure 5. The output capacitor is discharged through an internal 12 resistor connected between OUT2 and ground. Open-Drain Power-Good Output. PGOOD2 is low when the output voltage is more than 10% (typ) above or below the normal regulation point. PGOOD2 is also low during soft-start and shutdown. After the softstart circuit has terminated, PGOOD2 is high impedance if the output is in regulation. High-Side Gate-Driver Output for Controller 2. DH2 swings from LX2 to BST2. Inductor Connection for Controller 2. Connect to the switched side of the inductor. LX2 serves as the lower supply rail for the DH2 high-side gate driver. Boost Flying-Capacitor Connection for Controller 2. Connect to an external capacitor and diode as shown in Figure 6. An optional resistor in series with BST2 allows the DH2 pullup current to be adjusted. Power Ground Low-Side Gate-Driver Output for Controller 2. DL2 swings from PGND to VDD. Supply Voltage Input for the DL_ Gate Driver. Connect to the system supply voltage (+4.5V to +5.5V). Bypass VDD to power ground with a 1F or greater ceramic capacitor. Low-Side Gate-Driver Output for Controller 1. DL1 swings from PGND to VDD. Pulse-Skipping Control Input. This CMOS logic-level input enables or disables the light-load pulseskipping operation of both outputs. Connect SKIP as follows: VCC = OUT1 and OUT2 in forced-PWM mode. GND = OUT1 and OUT2 in pulse-skipping mode. Boost Flying-Capacitor Connection for Controller 1. Connect to an external capacitor and diode as shown in Figure 6. An optional resistor in series with BST1 allows the DH1 pullup current to be adjusted. Inductor Connection for Controller 1. Connect to the switched side of the inductor. LX1 serves as the lower supply rail for the DH1 high-side gate driver. High-Side Gate-Driver Output for Controller 1. DH1 swings from LX1 to BST1.
16
FB2
17
OUT2
18 19 21 22 23 24 26 27
PGOOD2 DH2 LX2 BST2 PGND DL2 VDD DL1
28
SKIP
29 30 32
BST1 LX1 DH1
12
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Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output
Pin Description (continued)
PIN NAME FUNCTION Open-Drain Power-Good Output. PGOOD1 is low when the output voltage is more than 10% (typ) above or below the normal regulation point. PGOOD1 is also low during soft-start and shutdown. After the softstart circuit has terminated, PGOOD1 becomes high impedance if the output is in regulation. For the MAX1549, PGOOD1 is blanked--forced high-impedance state--when FBLANK is enabled and the controller detects a transition on GATE. Output-Voltage Sense Connection for Controller 1. Connect directly to the positive terminal of the output capacitors as shown in the Standard Applications Circuit (Figure 1). OUT1 senses the output voltage to determine the on-time for the high-side switching MOSFET, and also serves as the feedback input. The output capacitor is discharged through an internal 12 resistor connected between OUT1 and ground. Negative Current-Sense Input for Controller 1. Connect to the negative terminal of the current-sense element. Figure 8 describes current-sensing options. The PWM controller does not begin a cycle unless the current sensed is less than the current-limit threshold programmed at ILIM1. Positive Current-Sense Input for Controller 1. Connect to the positive terminal of the current-sense element. Figure 8 describes current-sensing options. The PWM controller does not begin a cycle unless the current sensed is less than the current-limit threshold programmed at ILIM1.
MAX1549
33
PGOOD1
34
OUT1
35
CSL1
36
CSH1
37, 38, 39 40
OD1, OD2, Open-Drain Output. Controlled by G0 and G1 as described in Table 4. OD3 REFIN External Reference Input. REFIN sets the main output voltage (VOUT1 = VREFIN) of the MAX1549.
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Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output MAX1549
Table 1. Component Selection for Standard Applications
COMPONENT Input Voltage (VIN) G1 0 Output Voltage (VOUT) 0 1 1 Load Current Switching Frequency CIN_, Input Capacitor COUT_, Output Capacitor PWM1 5V to 16V G0 0 1 0 1 6A 300kHz (2) 10F, 25V Taiyo Yuden TMK432BJ106KM 470F, 4V, 10m Sanyo POSCAP 4TPD470M Siliconix Si4800BDY or Fairchild Semiconductor FDS6612A Siliconix Si4736DY or Fairchild Semiconductor FDS6670A 1A, 30V, 0.45Vf Nihon EP10QS03L 2.5H Sumida CDRH104-2R5NC 12m 1%, 0.5W resistor IRC LR2010-01-R012F or Dale WSL-2010-R012F 330F, 6.3V, 10m Sanyo POSCAP 6TPD330M Siliconix Si4800BDY or Fairchild Semiconductor FDS6612A Siliconix Si4736DY or Fairchild Semiconductor FDS6670A 1A, 30V, 0.45Vf Nihon EP10QS03L 4.7H Sumida CDRH124-4R7MC 15m 1%, 0.5W resistor IRC LR2010-01-R015F or Dale WSL-2010-R015F VOUT1 1.50V 1.30V 1.00V 0.70V 5A 300kHz 2.50V PWM2 5V to 16V
NH_ High-Side MOSFET
NL_ Low-Side MOSFET DL_ Schottky Rectifier (if needed) L_ Inductor
RCS_
14
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Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output MAX1549
Table 2. Component Suppliers
SUPPLIER AVX BI Technologies Central Semiconductor Coilcraft Coiltronics Fairchild Semiconductor International Rectifier Kemet Panasonic Sanyo Siliconix (Vishay) Sumida Taiyo Yuden TDK TOKO PHONE 843-448-9411 (USA) 714-447-2345 (USA) 631-435-1110 (USA) 800-322-2645 (USA) 561-752-5000 (USA) 888-522-5372 (USA) 310-322-3331 (USA) 408-986-0424 (USA) 800-344-2112 (USA) 81-72-870-6310 (Japan) 408-749-9714 (USA) 203-268-6261 (USA) 81-3-3667-3301 (Japan) 847-545-6700 (USA) 81-3-3833-5441 (Japan) 800-348-2496 (USA) 81-3-5201-7241 (Japan) 847-803-6100 (USA) 81-3-3727-1161 (Japan) 847-297-0070 (USA) www.avx.com www.bitechnologies.com www.centralsemi.com www.coilcraft.com www.coiltronics.com www.fairchildsemi.com www.irf.com www.kemet.com www.panasonic.com/industrial www.secc.co.jp www.vishay.com www.sumida.com www.t-yuden.com www.component.tdk.com www.tokoam.com WEBSITE
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15
Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output MAX1549
INPUT (VIN) 5V TO 16V CIN (2) 10F VDD DBST NH1 CBST 0.1F LX1 DL1 L1 2.5H NL1 PGND GND CSH1 RCS1 12m OUTPUT 1 VOUT1 = VREFIN COUT1 470F CREF 0.22F CCC1 470pF CC1 CSL1 OUT1 CSH2 RCS2 15m CSL2 OUT2 FB2 SKIP OUTPUT 2 VOUT2 = 2.5V COUT2 330F DL1 LX2 DL2 NL2 DL2 L2 4.7H DH1 BST1 DH2 BST2 CBST 0.1F DBST NH2
+5V BIAS SUPPLY
C1 1F
MAX1549
REF R2 100k ILIM1 R3 100k R4 100k ILIM2 R5 100k
FSEL ON1 ON2
OPEN (300kHz) ON OFF R1 20
VCC C2 1F R6 100k PGOOD1 PGOOD2 REFIN R10 66.5k OD3 R11 150k OD2 R12 487k R9 301k R8 100k R7 100k
+5V BIAS SUPPLY
POWER-GOOD REF
DYNAMIC OUT1 CONTROL INPUTS
G0 G1
OPEN (100s) POWER GROUND
FBLANK
OD1 CREFIN 470pF
ANALOG GROUND SEE TABLE 1 FOR COMPONENT SPECIFICATIONS.
Figure 1. Standard Applications Circuit 16 ______________________________________________________________________________________
Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output
Detailed Description
The MAX1549 dual fixed-frequency step-down controller designed for low-voltage power supplies is ideal for graphic processor units (GPUs). The Standard Applications Circuit (Figure 1) generates the dynamically adjustable output voltage (OUT1) typically required by graphics processor cores, and a fixed 2.5V output (OUT2) for the local memory used by the GPU. The MAX1549 main output supports up to four output voltages that can be dynamically selected for supporting multiple GPU frequency and sleep states. The interleaved, fixed-frequency architecture provides 180 out-of-phase operation to reduce the input capacitance required to meet the RMS input-current ratings. Each controller consists of a multi-input PWM comparator, high-side and low-side gate drivers, fault protection, power-good detection, adjustable current-limit circuitry, soft-start, and shutdown logic. The main PWM controller (OUT1) also includes a dedicated reference input; logicselected, open-drain outputs for dynamically adjusting the output voltage; and an integrator output for improved output-voltage accuracy. The second PWM controller (OUT2) includes a dual-mode feedback network and a multiplexer for preset 2.5V (FB2 = GND), 1.8V (FB2 = VCC), or adjustable output-voltage operation. See Table 1 for the standard applications circuit's component selection and Table 2 for component manufacturer contact information. The 5V bias supply must provide VCC (PWM controller) and VDD (gate-drive power), so the maximum current drawn is: IBIAS = ICC + fSW (QG(LOW) + QG(HIGH)) = 5mA to 50mA (typ) where ICC is 1mA (typ), fSW is the switching frequency, and Q G(LOW) and Q G(HIGH) are the MOSFET data sheet's total gate-charge specification limits at VGS = 5V. The battery input (VIN) and 5V bias inputs (VCC and VDD) can be connected together if the input source is a fixed 4.5V to 5.5V supply. If the 5V bias supply powers up prior to the battery supply, the enable signals (ON1 and ON2 going from low to high) must be delayed until the battery voltage is present to ensure startup.
MAX1549
Fixed-Frequency, Current-Mode PWM Controller
The heart of each current-mode PWM controller is a multi-input, open-loop comparator that sums two signals: the output-voltage error signal with respect to the reference voltage and the slope-compensation ramp (Figure 3). The MAX1549 uses a direct-summing configuration, approaching ideal cycle-to-cycle control over the output voltage without a traditional error amplifier and the phase shift associated with it. The MAX1549 uses a relatively low loop gain, allowing the use of lowcost output capacitors. The low loop gain results in the 0.1% (typ) load-regulation error and helps reduce the output-capacitor size and cost by shifting the unity-gain crossover frequency to a lower level. Integrator Amplifier (OUT1 Only) A feedback amplifier forces the DC average of the feedback voltage to equal the reference threshold voltage. This transconductance amplifier integrates the feedback voltage and provides a fine adjustment to the regulation voltage (Figure 2), allowing accurate DC output voltage regulation regardless of the output voltage ripple. The feedback amplifier has the ability to shift the output voltage by 8%. The differential input voltage range is at least 80mV total, including DC offset and AC ripple. Use a capacitor value of 47pF to 1000pF (470pF typ).
+5V Bias Supply (VCC and VDD)
The MAX1549 requires an external 5V bias supply in addition to the battery. Typically, this 5V bias supply is the notebook's 95% efficient, 5V system supply. Keeping the bias supply external to the IC improves efficiency and eliminates the cost associated with the 5V linear regulator that would otherwise be needed to supply the PWM circuit and gate drivers. If stand-alone capability is needed, generate the 5V bias supply with an external linear regulator (VIN > 5.5V) or regulated charge pump (VIN < 4.5V).
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Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output MAX1549
OSC FSEL SKIP ILIM2 ILIM1 CSH1 CSL1 BST1 DH1 LX1 VDD DL1 PGND FB2 DECODE (FIGURE 10) OUT2 FB2 PWM CONTROLLER 1 (FIGURE 3) PWM CONTROLLER 2 (FIGURE 3) CSH2 CSL2 BST2 DH2 LX2 VDD DL2
CC1 Gm ON2
OUT1 REF 3R 2.0V REF VCC GND
ON1
R REFIN
PGOOD1
POWER-GOOD AND FAULT PROTECTION (FIGURE 7)
POWER-GOOD AND FAULT PROTECTION (FIGURE 7)
PGOOD2
BLANK FBLANK G0 G1 GATE LOGIC QUAD-LEVEL DECODE AND TIMER
OD1
MAX1549
OD2
OD3
Figure 2. PWM-Controller Detailed Functional Diagram 18 ______________________________________________________________________________________
Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output MAX1549
CSH CSL FROM FB REF SLOPE COMP
0.1 x VLIMIT
R Q IDLE-MODE CURRENT S DH DRIVER
SKIP
SOFT-START ON COUNTER DAC
CURRENT LIMIT
OSC
S Q R LX
DL DRIVER
PGND
Figure 3. PWM-Comparator Functional Diagram ______________________________________________________________________________________ 19
Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output MAX1549
Table 3. FSEL Configuration
FSEL VCC Open REF GND SWITCHING FREQUENCY (kHz) 400 300 200 100
Light-Load Operation Control (SKIP)
The MAX1549 includes a light-load operating-mode control input (SKIP) used to independently enable or disable the zero-crossing comparator for both controllers. When the zero-crossing comparators are enabled (SKIP = GND), each controller forces DL_ low when its current-sense inputs detect zero inductor current. This keeps the inductor from discharging the output capacitors and forces the controller to skip pulses under light-load conditions to avoid overcharging the output. When the zero-crossing comparators are disabled (SKIP = VCC), each controller maintains PWM operation under light-load conditions (forced-PWM). The on-time of the step-down controller terminates when the output voltage exceeds the feedback threshold and when the current-sense voltage exceeds the idle-mode current-sense threshold. Under heavy-load conditions, the continuous inductor current remains above the idle-mode current-sense threshold, so the on-time depends only on the feedback-voltage threshold. Under light-load conditions, the controller remains above the feedback-voltage threshold, so the on-time duration depends solely on the idle-mode currentsense threshold, which is approximately 20% of the fullload current-limit threshold set by ILIM_. When transitioning from pulse-skipping mode to forcedPWM mode (SKIP rising edge), DL_ is pulled high immediately if both drivers are low. Idle-Mode Current-Sense Threshold The idle-mode current-sense threshold forces a lightly loaded regulator to source a minimum amount of power with each on-time. Since the zero-crossing comparator prevents the switching regulator from sinking current, the controller must skip pulses to avoid overcharging the output. When the clock edge occurs, if the output voltage still exceeds the feedback threshold, the controller does not initiate another on-time. This forces the controller to actually regulate the valley of the output voltage ripple under light-load conditions. Automatic Pulse-Skipping Crossover In skip mode, an inherent automatic switchover to PFM takes place at light loads (Figure 4). This switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current's zero crossing. The zero-crossing comparator differentially senses the inductor current across the low-side MOSFET (LX_ to PGND). Once V PGND - V LX _ drops below the 3mV zero-crossing current limit, the comparator forces DL_ low (Figure 3).
Frequency Selection (FSEL) The FSEL input selects the PWM-mode switching frequency as shown in Table 3. High-frequency (400kHz) operation optimizes the application for the smallest component size, trading off efficiency due to higher switching losses. This may be acceptable in ultraportable devices where the load currents are lower. Low-frequency (100kHz) operation offers the best overall efficiency at the expense of component size and board space.
Forced-PWM Mode
The low-noise forced-PWM mode disables the zerocrossing comparator, which controls the low-side switch on-time. This forces the low-side gate-drive waveform to be constantly the complement of the highside gate-drive waveform, so the inductor current reverses at light loads while DH_ maintains a duty factor of VOUT_ / VIN. The benefit of forced-PWM mode is keeping the switching frequency fairly constant. However, forced-PWM operation comes at a cost: the no-load 5V bias current remains between 5mA and 50mA, depending on the external MOSFETs and switching frequency. This additional supply current reduces the light-load efficiency. In particular, forced-PWM mode avoids audio-frequency noise under light-load conditions, improves the loadtransient response, and provides sink-current capability for dynamic output-voltage adjustments. The main MAX1549 controller (OUT1) uses forced-PWM operation during all dynamic output-voltage transitions (G0 or G1 transition detected) to ensure fast, accurate transitions. Since forced-PWM operation disables the zerocrossing comparator, the inductor current reverses under light loads, quickly discharging the output capacitors. FBLANK determines how long the main MAX1549 controller maintains forced-PWM operation-- 150s (FBLANK = VCC), 100s (FBLANK = open or GND), or 50s (FBLANK = REF).
20
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Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output
This mechanism causes the threshold between pulseskipping PFM and nonskipping PWM operation to coincide with the boundary between continuous and discontinuous inductor-current operation (also known as the "critical conduction" point). The load-current level at which the PFM/PWM crossover occurs, ILOAD(SKIP), is equal to 1/2 the idle-mode inductor current: ILOAD(SKIP) = 1 VIDLE 2 RSENSE
MAX1549
I = t INDUCTOR CURRENT
VIN - VOUT L
IIDLE
ILOAD = IIDLE / 2
where VIDLE is the idle-mode threshold (VIDLE = 0.2 x VLIMIT where VLIMIT = 0.1 x VILIM; see the Setting the Current Limit section). The switching waveforms may appear noisy and asynchronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. Tradeoffs in PFM noise vs. light-load efficiency are made by varying the inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming the coil resistance remains fixed) and less output voltage ripple. Penalties for using higher inductor values include larger size and degraded load-transient response (especially at low input-voltage levels).
0
ON-TIME
TIME
Figure 4. Pulse-Skipping/Discontinuous Crossover Point
For PFM operation (discontinuous conduction), the output voltage is defined by the following equation: VOUT(PFM ) = VNOM + 1 fSW IIDLE x ESR 2 fOSC
Output Voltage
DC-output accuracy specifications in the Electrical Characteristics table refer to the error-comparator threshold. When the inductor continuously conducts (PWM operation), the MAX1549 regulates the peak of the output ripple, so the actual DC output voltage depends on the error-comparator threshold, the slopecompensation amplitude, and the output voltage ripple. For PWM operation (continuous conduction), the output voltage is defined by the following equation:
ASLOPE VNOM VRIPPLE VOUT _(PWM ) = VNOM 1 - - VIN 2
where fOSC is the maximum switching frequency set by FSEL, fSW is the actual switching frequency, and IIDLE is the idle-mode inductor current when pulse skipping. Dynamic Output Voltages (OUT1 Only) The MAX1549 regulates OUT1 to the voltage set at REFIN. By changing the voltage at REFIN, the MAX1549 can be used in applications that require dynamic outputvoltage changes between two set points. Figure 1 shows a dynamically adjustable resistive voltage-divider network at REFIN. Using the G0 and G1 gate inputs and the open-drain outputs (OD1, OD2, and OD3), resistors can be switched in and out of the REFIN resistor-divider, dynamically changing the voltage at REFIN. The opendrain outputs are activated by the G0 and G1 gate inputs as shown in Table 4. The main output voltage is determined by the following equation: VOUT1 = VREF
REQ R8 + R EQ
where VNOM is the nominal output voltage, ASLOPE equals 1%, and VRIPPLE is the output voltage ripple (typically VRIPPLE = ESR x IINDUCTOR as described in the Output Capacitor Selection section). In discontinuous conduction (IOUT < ILOAD(SKIP)), the MAX1549 regulates the valley of the output ripple, and the output voltage has a DC regulation level higher than the error-comparator threshold by approximately 1.5% due to the slope compensation.
where REQ is the equivalent resistance between REFIN and ground (see Figure 1 and Table 4). The main MAX1549 controller (OUT1) automatically enters forced-PWM operation after detecting a G0 or G1 transition (rising or falling edge), and remains in forced-PWM mode for a minimum time selected by FBLANK (Table 5).
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21
Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output MAX1549
Table 4. Open-Drain Output States
INPUTS G1 0 0 1 1 G0 0 1 0 1 OD1 High-Z 0 High-Z High-Z OUTPUTS OD2 High-Z High-Z 0 High-Z OD3 High-Z High-Z High-Z 0 REQ R9 R9 // R12 R9 // R11 R9 // R10
Forced-PWM operation is required to ensure fast, accurate negative voltage transitions when REFIN is lowered. Since forced-PWM operation disables the zero-crossing comparator, the inductor current can reverse under light loads, quickly discharging the output capacitors. If fault blanking is enabled, the MAX1549 disables the main controller's (OUT1) output fault protection (OVP and UVP), and forces PGOOD1 to a high-impedance state for the period selected by FBLANK (Table 5). For a step voltage change at REFIN, the rate-of-change of the output voltage is limited by the inductor current ramp, the total output capacitance, the current limit, and the load during the transition. The inductor current ramp is limited by the voltage across the inductor and the inductance. The total output capacitance determines how much current is needed to change the output voltage. Additional load current slows down the output-voltage change during a positive REFIN voltage change, and speeds up the output-voltage change during a negative REFIN voltage change. Increasing the current-limit setting speeds up a positive output-voltage change.
Adding a capacitor across REFIN and GND filters noise and controls the rate-of-change of the REFIN voltage during dynamic transitions. With the additional capacitance, the REFIN voltage slews between the two set points with a time constant given by RREFIN x CREFIN, where RREFIN is the equivalent parallel resistance seen by the slew capacitor during the transition: R8 x REQ REFIN = CREFIN R8 + REQ Dual-Mode Feedback (OUT2 Only) The MAX1549's dual-mode operation allows the selection of common voltages without requiring external components (Figure 5). For the secondary controller (OUT2), connect FB2 to GND for a fixed 2.5V output, to VCC for a fixed 1.8V output, or connect FB2 directly to OUT2 for a fixed 0.5V output. The main controller (OUT1) of the MAX1549 regulates to the voltage set at REFIN (VFB1 = VREFIN) and does not support dualmode operation.
TO ERROR AMPLIFIER FB2 ADJUSTABLE OUTPUT
MAX1549
OUT2
FIXED OUTPUT (1.8V) FB = VCC
FIXED OUTPUT (2.5V) FB = GND
REF / 20
REF
Figure 5. Second Controller's Dual-Mode Feedback 22 ______________________________________________________________________________________
Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output
Alternately, the secondary output voltage (OUT2) can be adjusted from 0.5V to 2.7V using a resistive voltagedivider. The MAX1549 regulates FB2 to a fixed 0.5V reference voltage, so the secondary output voltage can be determined with the following equation: R VOUT2 = VFB2 1 + A RB where VFB2 = 0.5V, RA is the resistor from the output to FB2, and RB is the resistor from FB2 to analog ground. DL_ and DH_ drivers to the MOSFET gates for the adaptive dead-time circuits to work properly. Otherwise, the MAX1549 interprets the MOSFET gates as "off" while charge actually remains on the gate. Use very short, wide traces (50 mils to 100 mils wide if the MOSFET is 1in from the driver). The internal pulldown transistor that drives DL_ low is robust, with a 0.5 (typ) on-resistance. This helps prevent DL_ from being pulled up due to capacitive coupling from the drain to the gate of the low-side MOSFETs when the inductor node (LX_) quickly switches from ground to VIN. Applications with high input voltages and long, inductive driver traces may require additional gate-to-source capacitance to ensure fast-rising LX_ edges do not pull up the low-side MOSFETs' gate voltage, causing shootthrough currents. The capacitive coupling between LX_ and DL_ created by the MOSFETs' gate-to-drain capacitance (CRSS), gate-to-source capacitance (CISS - CRSS), and additional board parasitics should not exceed the following minimum threshold: C VGS( TH) > VIN RSS CISS Lot-to-lot variation of the threshold voltage can cause problems in marginal designs. Typically, adding a 4700pF between DL_ and power ground (CNL in Figure 6), close to the low-side MOSFETs, greatly reduces the voltage coupling. Do not exceed 22nF of total gate capacitance to prevent excessive turn-off delays. Alternately, shoot-through currents can be caused by a combination of fast high-side MOSFETs and slow lowside MOSFETs. If the turn-off delay time of the low-side MOSFET is too long, the high-side MOSFETs turn on before the low-side MOSFETs have actually turned off. Adding a resistor less than 10 in series with BST_ slows down the high-side MOSFET turn-on time, eliminating the shoot-through currents without degrading the turn-off time (Figure 6). Slowing down the high-side MOSFET also reduces the LX_ node rise time, thereby reducing the EMI and high-frequency coupling responsible for switching noise.
MAX1549
Current-Limit Protection (ILIM_)
The current-limit circuit uses differential current-sense inputs (CSH_ and CSL_) to limit the peak inductor current. If the magnitude of the current-sense signal exceeds the current-limit threshold, the PWM controller turns off the high-side MOSFET (Figure 3). At the next rising edge of the internal oscillator, the PWM controller does not initiate a new cycle unless the current-sense signal drops below the peak current-limit threshold. The actual maximum load current is less than the peak current-limit threshold by an amount equal to 1/2 the inductor ripple current. Therefore, the maximum load capability is a function of the current-limit threshold, current-sense resistance, inductor value, switching frequency, and duty cycle (VOUT / VIN). Connect ILIM_ to VCC for the 70mV default threshold, or adjust the current-limit threshold with an external resistordivider at ILIM_. Use a 2A to 20A divider current for accuracy and noise immunity. The current-limit threshold adjustment range is from 50mV to 200mV. In the adjustable mode, the current-limit threshold voltage equals precisely 1/10th the voltage seen at ILIM_ (VLIMIT = 0.1VILIM_). The logic threshold for switchover to the 70mV default value is approximately VCC - 1V. Carefully observe the PC board layout guidelines to ensure noise and DC errors do not corrupt the differential current-sense signals seen by CSH_ and CSL_. Place the IC close to the sense resistor with short, direct traces, making a Kelvin-sense connection to the current-sense resistor.
MOSFET Gate Drivers (DH_, DL_)
The DH_ and DL_ drivers are optimized for driving moderately sized, high-side and larger, low-side power MOSFETs. This is consistent with the low duty factor seen in notebook applications, where a large VIN - VOUT differential exists. An adaptive dead-time circuit monitors the DL_ output and prevents the high-side MOSFET from turning on until DL_ is fully off. A similar adaptive deadtime circuit monitors the DH_ output to prevent the lowside MOSFET from turning on until DH_ is fully off. There must be a low-resistance, low-inductance path from the
Power-Up Sequence
Power-on reset (POR) occurs when VCC rises above approximately 2V, resetting the fault latch and soft-start counter, powering up the reference, and preparing the PWM controllers for operation. Until VCC reaches 4.25V (typ), the VCC undervoltage-lockout (UVLO) circuitry inhibits switching. The controller inhibits switching by pulling DH_ low and forcing DL_ high. When VCC rises above 4.25V and ON_ is driven high, the activated controller initializes soft-start and starts switching.
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Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output MAX1549
Soft-Shutdown
Soft-shutdown slowly discharges the output capacitance, providing a damped shutdown response. This eliminates the slightly negative output voltages caused by quickly discharging the output through the inductor and low-side MOSFET. Both controllers contain separate soft-shutdown circuits. When the controller is disabled--ON_ pulled low, the UV fault latch set, or input UVLO triggered--the MAX1549 discharges the respective output through an internal 12 switch to ground. While the output discharges, the MAX1549 forces DL_ low and disables the PWM controller, but the reference remains active to provide an accurate threshold. Once the output voltage drops below 0.3V, the MAX1549 pulls DL_ high, effectively clamping the output and LX_ switching node to ground. The reference shuts down once both outputs are disabled and discharged below 0.3V.
CBYP
MAX1549
VDD (RBST)* CBST DH NH L DBST
BST
INPUT (VIN)
LX VDD DL (CNL)* GND NL
Power-Good Output (PGOOD_)
The MAX1549 includes separate open-drain outputs for the power-good window comparators (Figure 7) that monitor each output continuously (except during mainoutput fault blanking; see the Fault and Power-Good Blanking section). The controller actively holds PGOOD_ low in shutdown and during soft-start. Once the digital soft-start terminates, PGOOD_ becomes high impedance as long as the respective output voltage is within 10% of the nominal regulation voltage. When either output voltage drops 10% below or rises 10% above the nominal regulation voltage, the MAX1549 pulls the respective PGOOD_ output low. Any fault condition forces both PGOOD1 and PGOOD2 low until the fault latch is cleared by toggling ON1 or ON2, or cycling VCC power below 1V. For logic-level output voltages, connect an external pullup resistor between PGOOD_ and VCC. A 100k resistor works well in most applications. The power-good window comparators are completely independent of the overvoltage and undervoltage-protection fault comparators.
(RBST)* OPTIONAL--THE RESISTOR LOWERS EMI BY DECREASING THE SWITCHING-NODE RISE TIME. (CNL)* OPTIONAL--THE CAPACITOR REDUCES LX TO DL CAPACITIVE COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS.
Figure 6. Optional Gate-Driver Circuitry
Digital Soft-Start
Soft-start allows a gradual increase of the internal current-limit level during startup to reduce the input surge currents. Both controllers contain an internal digital soft-start circuit. In shutdown mode or input UVLO, the controller resets the soft-start counter to zero. The MAX1549 divides the soft-start period into five phases. During the first phase, the controller limits the peak current limit to only 20% of the full current limit. If the output does not reach regulation within 128 clock cycles (1 / fOSC), soft-start enters the second phase and increments the current limit by another 20%. This process repeats until soft-start reaches the maximum current limit after 512 clock cycles or until the output reaches the nominal regulation voltage, whichever occurs first (see the Soft-Start Waveforms in the Typical Operating Characteristics). The exact rise time of the output voltage depends on the output capacitance and load current.
Fault Protection
Overvoltage Protection (OVP) If either output voltage rises above 114.5% of its nominal regulation voltage, the OVP circuit sets the fault latch, pulls PGOOD1 and PGOOD2 low, shuts down both PWM controllers, and immediately pulls DH_ low and forces DL_ high. This turns on the synchronousrectifier MOSFETs with 100% duty, rapidly discharging the output capacitors and clamping both outputs to ground. However, immediately latching DL_ high typically causes slightly negative output voltages due to
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Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output MAX1549
POWER-GOOD 0.9 x INT REF 1.1 x INT REF FAULT PROTECTION 0.7 x INT REF 1.14 x INT REF INTERNAL FB
Table 5. FBLANK Configuration Table
FBLANK VCC Open REF GND
BLANK (TRANSITION)
OUT1 FAULT AND PGOOD1 BLANKING Enabled (150s) Enabled (100s) Enabled (50s) Disabled
OUT1 FORCED-PWM DURATION (TYP) (s) 150 100 50 100
Fault and Power-Good Blanking (FBLANK)
The main MAX1549 controller (OUT1) automatically enters forced-PWM operation during all dynamic output-voltage transitions (G0 or G1 transition detected) to ensure fast, accurate transitions. FBLANK determines how long the main controller maintains forced-PWM operation (Table 5)--150s (FBLANK = VCC), 100s (FBLANK = open or GND), or 50s (FBLANK = REF). When fault blanking is enabled (FBLANK = VCC, open, or REF), the MAX1549 also disables the overvoltage and undervoltage fault protection for OUT1, and forces PGOOD1 to a high-impedance state during the transition period selected by FBLANK (Table 5). This prevents fault protection from latching off the MAX1549 and keeps the PGOOD1 signal from going low while the output-voltage transition occurs.
TIMER
FAULT LATCH
FAULT POWER-GOOD
POR
Figure 7. Power-Good and Fault Protection
the energy stored in the output LC at the instant the OV fault occurs. If the load cannot tolerate a negative voltage, place a power Schottky diode across the output to act as a reverse-polarity clamp. If the condition that caused the overvoltage persists (such as a shorted high-side MOSFET), the battery fuse blows. The main controller temporarily blanks OVP after transitions are detected on G0 or G1 (FBLANK enabled). Toggle ON1 or ON2, or cycle VCC power below 1V, to clear the fault latch and restart the controller. Undervoltage Protection (UVP) Each controller has an output UVP circuit that activates 4096 clock cycles (1 / f OSC ) after the controller is enabled. If either output voltage drops below 70% of its nominal regulation voltage, the MAX1549 sets the fault latch, pulls PGOOD1 and PGOOD2 low, and shuts down both controllers using discharge mode (see the Soft-Shutdown section). When each output voltage drops to 0.3V, its synchronous rectifier turns on and clamps the output to GND. The main controller temporarily blanks UVP after transitions are detected on G0 or G1 (FBLANK enabled). Toggle ON1 or ON2, or cycle VCC power below 1V, to clear the fault latch and restart the controller. Thermal Fault Protection The MAX1549 features a thermal fault-protection circuit. When the junction temperature rises above +160C, a thermal sensor activates the fault latch, pulls PGOOD1 and PGOOD2 low, and shuts down both controllers using discharge mode. Toggle ON1 or ON2, or cycle VCC power below 1V, to reactivate the controller after the junction temperature cools by 15C.
Design Procedure
Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design tradeoff lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: Input Voltage Range: The maximum value (VIN(MAX)) must accommodate the worst-case, high AC-adapter voltage. The minimum value (VIN(MIN)) must account for the lowest battery voltage minus the voltage drops associated with the connectors, fuses, and battery-selector switches. If there is a choice at all, lower input voltages result in better efficiency. The minimum and maximum input voltage range is restricted by the minimum and maximum duty-cycle limits specified in the Electrical Characteristics table: V VOUT VIN(MIN) > OUT and VIN(MAX) < DMAX t ON(MIN)fOSC where D MAX is the 91% maximum duty-cycle limit, tON(MIN) is the 200ns minimum off-time, and fOSC is the switching frequency selected by FSEL. Since the maximum input voltage range is restricted by the switching frequency and output voltage, lower frequency operation might be required for high input-to-output voltage applications.
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Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output
Maximum Load Current: There are two values to consider. The peak inductor current (IPEAK) determines the instantaneous component stresses and filtering requirements and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The maximum continuous load current (ILOAD(MAX)) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components. Switching Frequency: This choice determines the basic tradeoff between size, efficiency, and maximum input voltage range. The optimum frequency is largely a function of maximum input voltage, due to MOSFET switching losses that are proportional to frequency and VIN2. The optimum frequency is also a moving target, due to rapid improvements in MOSFET technology that are making higher frequencies more practical. Inductor Operating Point: This choice provides tradeoffs between size vs. efficiency and transient response vs. output ripple. Low inductor values provide better transient response and smaller size, but also result in lower efficiency and higher output ripple due to increased ripple currents. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further size-reduction benefit. The optimum operating point is usually found between 20% and 50% ripple current. When pulse skipping (SKIP low and light loads), the inductor value also determines the loadcurrent value at which PFM/PWM switchover occurs.
MAX1549
Find a low-loss inductor with the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK): LIR IPEAK = ILOAD(MAX) 1 + 2 Most inductor manufacturers provide inductors in standard values, such as 1.0H, 1.5H, 2.2H, 3.3H, etc. Also look for nonstandard values, which can provide a better compromise in LIR across the input voltage range. If using a swinging inductor (where the no-load inductance decreases linearly with increasing current), evaluate the LIR with properly scaled inductance values.
Transient Response
The inductor ripple current also impacts transientresponse performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output-filter capacitors by a sudden load step. The total output voltage sag is the sum of the voltage sag while the inductor is ramping up and the voltage sag before the next pulse can occur: VSAG = 2COUT (VIN x DMAX - VOUT ) ILOAD(MAX) (T - T COUT L ILOAD(MAX)
(
)2
)
Inductor Selection
The switching frequency and inductor operating point determine the inductor value as follows: L= VOUT ( VIN - VOUT ) VIN x fOSC x ILOAD(MAX) x LIR
+
For example: I LOAD(MAX) = 5A, V IN = 12V, V OUT = 2.5V, fOSC = 300kHz, 30% ripple current or LIR = 0.3: 2.5V x (12V - 2.5V) L= = 4.40H 12V x 300kHz x 5A x 0.3
where D MAX is the maximum duty factor (see the Electrical Characteristics table), T is the cycle period (1 / fOSC), T equals VOUT / VIN x T when in PWM mode, or L x 0.2 x IMAX / (VIN - VOUT) when in skip mode. The amount of overshoot during a full-load to no-load transient due to stored inductor energy can be calculated as: VSOAR
(ILOAD(MAX) )2L
2COUT VOUT
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Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output
Setting the Peak Current Limit
The minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. The peak inductor current occurs at ILOAD(MAX) plus 1/2 the ripple current; therefore: ILOAD(MAX)LIR ILIMIT > ILOAD(MAX) + 2 where ILIMIT_ equals the minimum current-limit threshold voltage divided by the current-sense resistance (RSENSE). For the 70mV default setting, the minimum current-limit threshold is 65mV. Connect ILIM_ to VCC for a default 70mV current-limit threshold. In adjustable mode, the current-limit threshold is precisely 1/10th the voltage seen at ILIM_. For an adjustable threshold, connect a resistive-divider from REF to analog ground (GND) with ILIM_ connected to the center tap. The external 500mV to 2V adjustment range corresponds to a 50mV to 200mV current-limit threshold. When adjusting the current limit, use 1% tolerance resistors and a divider current of approximately 10A to prevent significant inaccuracy in the currentlimit tolerance. The current-sense method (Figure 8) and magnitude determine the achievable current-limit accuracy and power loss. Typically, higher current-sense limits provide more noise immunity, but also dissipate more power. Most applications employ a current-limit threshold (VLIMIT) of 50mV to 100mV, so the sense resistor can be determined by: V RSENSE = LIMIT ILIMIT For the best current-sense accuracy and overcurrent protection, use a 1% tolerance current-sense resistor between the inductor and output as shown in Figure 8A. This configuration constantly monitors the inductor current, allowing accurate current-limit protection. Alternately, high-power applications that do not require highly accurate current-limit protection can reduce the overall power dissipation by connecting a series RC circuit across the inductor (Figure 8B) with an equivalent time constant: L = CEQL x REQL RDCR where RDCR is the inductor's series DC resistance. In this configuration, the current-sense resistance equals
INPUT (VIN) CIN
MAX1549
MAX1549
DH_ LX_ DL_ PGND
NH L RSENSE COUT DL
NL
CSH_ CSL_
A) OUTPUT SERIES RESISTOR SENSING
INPUT (VIN) CIN
MAX1549
DH_ LX_ DL_ PGND
NH INDUCTOR
NL
DL
REQL
CEQL
COUT
CSH_ CSL_
RBIAS = REQL
B) LOSSLESS INDUCTOR SENSING
Figure 8. Current-Sense Configurations
the inductor's DC resistance (RSENSE = RDCR). Use the worst-case inductance and RDCR values provided by the inductor manufacturer, adding some margin for the inductance drop over temperature and load.
Output Capacitor Selection
The output-filter capacitor must have low enough equivalent series resistance (ESR) to meet output ripple and load-transient requirements, yet have high enough ESR to satisfy stability requirements. For processor core voltage converters and other applications where the output is subject to severe load transients, the output capacitor's size depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance: RESR VSTEP ILOAD(MAX)
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Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output
In applications without large and fast load transients, the output capacitor's size often depends on how much ESR is needed to maintain an acceptable level of output voltage ripple. The output voltage ripple of a step-down controller equals the total inductor ripple current multiplied by the output capacitor's ESR. Therefore, the maximum ESR required to meet the ripple specifications is: VRIPPLE RESR ILOAD(MAX)LIR The actual capacitance value required relates to the size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value (this is true of tantalums, OS-CONs, polymers, and other electrolytics). When using low-capacity filter capacitors, such as ceramic capacitors, size is usually determined by the capacity needed to prevent V SAG and V SOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the VSAG and VSOAR equations in the Transient Response section). However, lowcapacity filter capacitors typically have high ESR zeros that can affect the overall stability (see the OutputCapacitor Stability Considerations section). Do not put high-value ceramic capacitors directly across the feedback sense point without taking precautions to ensure stability. Large ceramic capacitors can have a high-ESR zero frequency and cause erratic, unstable operation. However, it is easy to add enough series resistance by placing the capacitors a couple inches downstream from the feedback sense point, which should be as close as possible to the inductor. Unstable operation manifests itself in two related but distinctly different ways: duty-cycle variation and fastfeedback loop instability. Duty-cycle variation occurs due to noise on the output or because the ESR is so low that there is not enough voltage ramp in the outputvoltage signal. This "fools" the error comparator into extending the on-time, forcing the next cycle to terminate its on-time early. Duty-cycle variation is more annoying than harmful, resulting in nothing worse than increased output ripple. However, it can indicate the possible presence of loop instability due to insufficient ESR. Loop instability can result in oscillations at the output after line or load steps. Such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits. The easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output-voltage-ripple envelope for overshoot and ringing. It can help to simultaneously monitor the inductor current with an AC current probe. Do not allow more than one cycle of ringing after the initial step-response under/overshoot.
MAX1549
Output-Capacitor Stability Considerations
The MAX1549 controllers rely on the output voltage ripple, which can be defined as the inductor current ripple times the output capacitor's ESR, to generate the current-mode control signal required for stable operation. Therefore, the controller's stability is determined by the value of the ESR zero relative to the switching frequency. The boundary of instability is given by the following equation: f fESR OSC where: fESR = 1 2RESR COUT
Input Capacitor Selection
The input capacitor must meet the RMS ripple current requirement (IRMS) imposed by the switching currents. For a single step-down converter, the RMS input ripple current is defined by the output load current (IOUT), input voltage, and output voltage, with the worst-case condition occurring at VIN = 2VOUT: V OUT (VIN - VOUT ) IRMS = IOUT VIN For a dual 180 interleaved controller, the out-of-phase operation reduces the RMS input ripple current, effectively lowering the input capacitance requirements.
For a typical 300kHz application, the ESR zero frequency must be well below 95kHz, preferably below 50kHz. Tantalum and OS-CON capacitors in widespread use at the time of publication have typical ESR zero frequencies of 25kHz. In the design example used for inductor selection, the ESR needed to support 25mVP-P ripple is 25mV / 1.5A = 16.7m. One 220F/4V Sanyo polymer (TPE) capacitor provides 15m (max) ESR. This results in a zero at 48kHz, well within the bounds of stability.
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Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output
When both outputs operate with a duty cycle less than 50% (VIN > 2VOUT), the RMS input ripple current is defined by the following equation: VOUT1 V IOUT1(IOUT1 - IIN ) IN V + OUT2 IOUT2 (IOUT2 - IIN ) VIN
Power MOSFET Dissipation
Worst-case conduction losses occur at the duty-factor extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at minimum input voltage: V 2 PD (NH Re sistive) = OUT (ILOAD ) RDS(ON) VIN Generally, use a small high-side MOSFET to reduce switching losses at high input voltages. However, the RDS(ON) required to stay within package power-dissipation limits often limits how small the MOSFET can be. The optimum occurs when the switching losses equal the conduction (RDS(ON)) losses. High-side switching losses do not become an issue until the input is greater than approximately 15V. Calculating the power dissipation in high-side MOSFETs (NH) due to switching losses is difficult since it must allow for difficult-to-quantify factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PC-boardlayout characteristics. The following switching loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on NH: PD (NH Switching) =
MAX1549
IRMS =
where IIN is the average input current: V V IIN = OUT1 IOUT1 + OUT2 IOUT2 VIN VIN For most applications, nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their resilience to power-up surge currents typical of systems with a mechanical switch or connector in series with the input. If the MAX1549 is operated as the second stage of a two-stage power-conversion system, tantalum input capacitors are acceptable. In either configuration, choose a capacitor that has less than 10C temperature rise at the RMS input current for optimal reliability and lifetime.
Power MOSFET Selection
Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (>20V) AC adapters. Low-current applications usually require less attention. The high-side MOSFET (NH) must be able to dissipate the resistive losses plus the switching losses at both VIN(MIN) and VIN(MAX). Ideally, the losses at VIN(MIN) should be roughly equal to the losses at VIN(MAX), with lower losses in between. If the losses at VIN(MIN) are significantly higher, consider increasing the size of NH. Conversely, if the losses at VIN(MAX) are significantly higher, consider reducing the size of NH. If VIN does not vary over a wide range, maximum efficiency is achieved by selecting a high-side MOSFET (N H) that has conduction losses equal to the switching losses. Choose a low-side MOSFET (NL) that has the lowest possible on-resistance (RDS(ON)), comes in a moderate-sized package (i.e., 8-pin SO, DPAK, or D2PAK), and is reasonably priced. Ensure that the MAX1549 DL_ gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic drain-to-gate capacitor caused by the high-side MOSFET turning on; otherwise, cross-conduction problems can occur. Switching losses are not an issue for the low-side MOSFET since it is a zero-voltage switched device when used in the step-down topology.
(VIN(MAX) )2 CRSSfSWILOAD
IGATE
where CRSS is the reverse transfer capacitance of NH, and IGATE is the peak gate-drive source/sink current (1A typ). Switching losses in the high-side MOSFET can become a heat problem when maximum AC-adapter voltages are applied, due to the squared term in the switchingloss equation (C x VIN2 x fSW). If the high-side MOSFET chosen for adequate RDS(ON) at low battery voltages becomes extraordinarily hot when subjected to V IN(MAX) , consider choosing another MOSFET with lower parasitic capacitance. For the low-side MOSFET (NL), the worst-case power dissipation always occurs at maximum battery voltage:
V 2 PD (NL Re sistive) = 1 - OUT (ILOAD ) RDS(ON) VIN(MAX)
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Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output MAX1549
The absolute worst case for MOSFET power dissipation occurs under heavy overload conditions that are greater than ILOAD(MAX) but are not high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, "overdesign" the circuit to tolerate: ILOAD(MAX)LIR ILOAD = ILIM - 2 where ILIM is the peak current allowed by the current-limit circuit, including threshold tolerance and sense-resistance variation. The MOSFETs must have a relatively large heatsink to handle the overload power dissipation. Choose a Schottky diode (DL) with a forward-voltage drop low enough to prevent the low-side MOSFET's body diode from turning on during the dead time. As a general rule, select a diode with a DC current rating equal to 1/3rd the load current. This diode is optional and can be removed if efficiency is not critical.
Applications Information
Duty-Cycle Limits
Minimum Input Voltage The minimum input operating voltage (dropout voltage) is restricted by the maximum duty-cycle specification (see the Electrical Characteristics table). However, keep in mind that the transient performance gets worse as the step-down regulators approach the dropout voltage, so bulk output capacitance must be added (see the voltage sag and soar equations in the Design Procedure section). The absolute point of dropout occurs when the inductor current ramps down during the off-time (IDOWN) as much as it ramps up during the on-time (IUP). This results in a minimum operating voltage defined by the following equation:
1 VIN(MIN) = VOUT + VCHG + h - 1 ( VOUT + VDIS ) DMAX
Boost Capacitors
The boost capacitors (CBST) must be selected large enough to handle the gate-charging requirements of the high-side MOSFETs. Typically, 0.1F ceramic capacitors work well for low-power applications driving medium-sized MOSFETs. However, high-current applications driving large, high-side MOSFETs require boost capacitors larger than 0.1F. For these applications, select the boost capacitors to avoid discharging the capacitor more than 200mV while charging the highside MOSFETs' gates: CBST = N x QGATE 200mV
where VCHG and VDIS are the parasitic voltage drops in the charge and discharge paths, respectively. A reasonable minimum value for h is 1.5, while the absolute minimum input voltage is calculated with h = 1. Maximum Input Voltage The MAX1549 controller includes a minimum on-time specification, which determines the maximum input operating voltage that maintains the selected switching frequency (see the Electrical Characteristics table). Operation above this maximum input voltage results in pulse-skipping operation, regardless of the operating mode selected by SKIP. At the beginning of each cycle, if the output voltage is still above the feedbackthreshold voltage, the controller does not trigger an ontime pulse, effectively skipping a cycle. This allows the controller to maintain regulation above the maximum input voltage, but forces the controller to effectively operate with a lower switching frequency. This results in an input-threshold voltage at which the controller begins to skip pulses (VIN(SKIP)): 1 VIN(SKIP) = VOUT fOSC t ON(MIN) where fOSC is the switching frequency selected by FSEL.
where N is the number of high-side MOSFETs used for one regulator, and QGATE is the gate charge specified in the MOSFET's data sheet. For example, assume one IRF7811W N-channel MOSFET is used on the high side. According to the manufacturer's data sheet, a single IRF7811W has a maximum gate charge of 24nC (VGS = 5V). Using the above equation, the required boost capacitance is: CBST = 1 x 24nC = 0.12F 200mV
Selecting the closest standard value, this example requires a 0.1F ceramic capacitor.
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Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output MAX1549
C1 1F +5V BIAS SUPPLY R1 20 VCC C2 1F SKIP VDD DBST DH2 BST2 CBST LX2 R7 R6 PGOOD1 POWER-GOOD PGOOD2 GND CSH2 RCS2 CREF 0.22F REF R2 ILIM1 R3 R4 DH1 ILIM2 R5 BST1 CBST OUT2 R8 REFIN R9 C3 CSH1 RCS1 CSL1 FBLANK OD3 UNUSED OD2 0D1 FSEL G0 G1 ON1 ON2 ON OFF OPEN (300kHz) CC1 OUT1 CCC1 470pF COUT1 OUTPUT 1 VTT = VDDQ/2 LX1 DL1 NL1 DL1 L1 DBST NH1 DL2 PGND NL2 DL2 L2 NH2
INPUT (VIN)
MAX1549
CSL2 OUT2 FB2 VDD COUT2 OUTPUT 2 VDDQ = 2.5V
POWER GROUND
ANALOG GROUND
Figure 9. Active Bus Termination ______________________________________________________________________________________ 31
Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output MAX1549
Active Bus Termination (OUT1)
Active-bus-termination power supplies generate a voltage rail that tracks a set reference. They are required to source and sink current. DDR memory architecture requires active bus termination. In DDR memory architecture, the termination voltage is set at exactly 1/2 the memory supply voltage. Configure the main MAX1549 controller (OUT1) to generate the termination voltage using a resistive voltage-divider at REFIN. In such an application, OUT1 must be kept in PWM mode (SKIP = VCC or open) for it to source and sink current. Figure 9 shows OUT1 configured as a DDR termination regulator. Connect GATE and FBLANK to GND when unused. Figure 10 shows the connection of OUT_ and FB_ in voltage-positioned and nonvoltage-positioned circuits. In nonvoltage-positioned circuits, the MAX1549 regulates the voltage across the output capacitor. In voltage-positioned circuits, the MAX1549 regulates the voltage on the inductor side of the current-sense resistor. The voltagepositioned output voltage is reduced to: VOUT(VPS) = VOUT(NO LOAD) - RSENSEILOAD For a conventional (nonvoltage-positioned) circuit, the peak-to-peak voltage change is: VOUT(CONV) = 2 x (ESRCOUT x ILOAD) + VSAG + VSOAR where V SAG and V SOAR are defined in Figure 11. Setting the converter to regulate at a lower voltage when under load allows a larger voltage step when the output current suddenly decreases. Therefore, the peak-to-peak voltage change for a voltage-positioned circuit is: VOUT(VPS) = (ESRCOUT x ILOAD) + VSAG + VSOAR where V SAG and V SOAR are defined in the Design Procedure section. Since the amplitudes are the same for both circuits (VOUT(CONV) = VOUT(VPS)), the voltage-positioned circuit tolerates twice the ESR. Since the ESR specification is achieved by paralleling several capacitors, fewer units are needed for the voltage-positioned circuit.
Voltage Positioning
Powering new mobile processors (CPU or GPU) requires careful attention to detail to reduce cost, size, and power dissipation. As processors consume more power, it was recognized that even the fastest DC-DC converters were inadequate to handle the severe transient power requirements. After a load transient, the output instantly changes by ESR COUT x I LOAD . Conventional DC-DC converters respond by regulating the output voltage back to its nominal state after the load transient occurs (Figure 11), but the processor only requires that the output voltage remains above a specified minimum value. Dynamically positioning the output voltage to this lower limit allows the use of fewer output capacitors and reduces the power consumption under load.
R1
+5V BIAS SUPPLY C2
VCC C1
VDD DBST V+ BST NH DH CBST L1 CIN REGULATED VOLTAGE RSENSE VOLTAGE-POSITIONED OUTPUT (VOUT(VPS)) COUT INPUT (VIN)
MAX1549
LX NL DL GND DL
CSH OUT CSL
FB
VOUT(VPS) = VOUT(NO LOAD) - RSENSE x IOUT
Figure 10. Voltage-Positioned Applications Circuit 32 ______________________________________________________________________________________
Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output MAX1549
VOLTAGE POSITIONING THE OUTPUT
CAPACITIVE SOAR (dV/dt = IOUT / COUT) ESR VOLTAGE STEP (ISTEP x RESR) A
1.4V
VOUT
1.4V B
CAPACITIVE SAG (dV/dt = IOUT / COUT)
RECOVERY
A. CONVENTIONAL CONVERTER (50mV/div) B. VOLTAGE-POSITIONED OUTPUT (50mV/div)
ILOAD
Figure 11. Voltage-Positioning Transient Response
An additional benefit of voltage positioning is reduced power consumption at high load currents. Since the output voltage is lower under load, the processor draws less current. The result is lower power dissipation in the processor, although extra power is dissipated in the current-sense element. However, the current-sense element used for current-limit protection can also be used for voltage positioning, further reducing the overall power dissipation. In effect, the processor's power dissipation is saved and the power supply dissipates some of the savings, but both the net savings and the transfer of dissipation away from the hot processor are beneficial.
approached in terms of fractions of centimeters, where a single m of excess trace resistance causes a measurable efficiency penalty. * When tradeoffs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor. Minimize current-sensing errors by connecting CSH_ and CSL_ directly across the current-sense resistor (RSENSE_). Route all high-speed switching nodes (BST_, LX_, DH_, and DL_) away from sensitive analog areas (REF, FB_, CSH_, and CSL_).
*
PC Board Layout Guidelines
Careful PC board layout is critical to achieving low switching losses and clean, stable operation. The switching power stage requires particular attention (Figure 12). If possible, mount all the power components on the top side of the board, with their ground terminals flush against one another. Refer to the MAX1549 evaluation kit data sheet for a specific layout example. Follow these guidelines for good PC board layout: * Use a star-ground connection on the power ground plane to minimize the crosstalk between OUT1 and OUT2. Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation. Keep the power traces and load connections short. This practice is essential for high efficiency. Using thick copper PC boards (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. Correctly routing PC board traces is a difficult task that must be *
Layout Procedure
1) Place the power components first, with ground terminals adjacent (NL_ source, CIN, COUT_, and DL_ anode). If possible, make all these connections on the top layer with wide, copper-filled areas. 2) Mount the controller IC adjacent to the low-side MOSFET, preferably on the back side opposite NL_ and NH_ to keep LX_, DH_, and the DL_ gate-drive lines short and wide. The DL_ and DH_ gate traces must be short and wide (50 mils to 100 mils wide if the MOSFET is 1in from the controller IC) to keep the driver impedance low and for proper adaptive dead-time sensing.
*
*
______________________________________________________________________________________
33
Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output MAX1549
3) Group the gate-drive components (BST_ diode and capacitor, VDD bypass capacitor) together near the controller IC. 4) Make the DC-DC controller ground connections as shown in Figures 1 and 12. These diagrams can be viewed as having two separate ground planes: power ground for the high-power components, and an analog ground plane for sensitive analog components. These separate ground planes must meet only at a single point directly at the IC. Additionally, a star-ground connection (centered at PGND) must be used on the power ground plane to minimize any crosstalk between the two controllers. 5) Connect the output power planes directly to the output-filter-capacitor positive and negative terminals with multiple vias. Place the entire DC-DC converter circuit as close to the load as is practical.
Chip Information
TRANSISTOR COUNT: 8823 PROCESS: BiCMOS
VIA TO ANALOG GROUND PLANE VIA TO 5V BIAS SUPPLY (VDD)
VIA TO VCC BYPASS CAPACITOR
VIA TO POWER GROUND MAX1549 TOP LAYER CONNECT GND AND PGND TO THE CONTROLLER AT ONE POINT ONLY AS SHOWN
CONNECT THE EXPOSED PAD TO ANALOG GND
KELVIN-SENSE VIAS UNDER THE SENSE RESISTOR (REFER TO THE EVALUATION KIT) DUAL N-CHANNEL MOSFET
INDUCTOR
SINGLE N-CHANNEL MOSFETS
INDUCTOR
DH LX DL COUT CIN COUT INPUT OUTPUT OUTPUT OUTPUT GROUND COUT GROUND CIN INPUT HIGH-POWER LAYOUT
LOW-POWER LAYOUT
Figure 12. PC Board Layout Example 34 ______________________________________________________________________________________
Dual, Interleaved, Fixed-Frequency Step-Down Controller with a Dynamically Adjustable Output
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QFN THIN 6x6x0.8.EPS
MAX1549
D2 D D/2 k
C L
b D2/2
E/2 E2/2 E (NE-1) X e
C L
E2
k
e (ND-1) X e
L
e L
C L C L
L1 L L
e
e
A1
A2
A
PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm
21-0141
E
1 2
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1. 10. WARPAGE SHALL NOT EXCEED 0.10 mm.
PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm
21-0141
E
2 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 35 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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